This invention relates to a semiconductor integrated circuit, and to techniques which are particularly effective when utilized for, for example, a bipolar-CMOS (hereinbelow, abbreviated to "Bi-CMOS") gate array.
A Bi-CMOS complex logic gate circuit which comprises in combination a pair of output bipolar transistors in a totem pole form and a CMOS (complementary MOS) logic gate circuit, has both a comparatively high drivability and a low power consumption property.
Therefore, Bi-CMOS logic gates have come to be applied to various semiconductor devices, for example, gate array devices and memory devices and to microcomputers (refer to IEEE Journal of SOLID-STATE CIRCUITS, Vol. 23, No. 1, February 1988, pp. 5-11).
In this regard, a gate array employing Bi-CMOS logic gates is disclosed in the official gazette of Japanese Patent Application Laid-open No. 59-139724 (corresponding U.S. Pat. No. 4,689,503, corresponding Korean Patent Application No. 1983-5666, and corresponding British Patent No. 2135148).
Besides, basic cells for use in Bi-CMOS gate array devices are described in the official gazette of Japanese Patent Application Laid-open No. 61-171150 (corresponding U.S. Pat. Ser. No. 822,786, corresponding Korean Patent Application No. 1985-9158, and corresponding European Patent Application Laid-open No. 0.189.183A1), the official gazette of Japanese Patent Application Laid-open No. 59-193627 (corresponding U.S. Pat. Ser. No. 600,965, and corresponding European Patent Application Laid-open No. 0.125.504A1), "AMCC's BiCMOS ARRAY HITS RECODE GATE UTILIZATION" published in Electronics/Feb. 4, 1988, pp. 65-66 by Bernard C. Cole, and "Low Power High Speed BiCMOS Gate-Array" published in NEC Technical Bulletin, Vol. 39, No. 10/1986, pp. 138-143 by Nakashiba et al.
Incidentally, the "gate array" is a semiconductor integrated circuit device of the so-called master slice method according to which many kinds of semiconductor integrated circuit devices can be realized in such a way that master wafers prepared in large amounts beforehand are merely subjected to the wiring steps of the respective kinds of articles. This method has such advantages as the reduction of cost based on the mass production of the master wafers and the shortening of a development period based on the automatic design of wiring and the short manufacturing process of only the wiring operation.